Friday 10 April 2015

Lab Power Supply Project - Voltage Regulator

I thought to begin with I would design the voltage regulator part of the lab supply. I can get this working independently of everything else pretty much. The regulator will set the output voltage between 0-30V (from a 30V, 160VA transformer) at 3A or 0-15 at 5A.

Bulk Capacitor

The bulk charge storage capacitors(s) determine the ripple and therefore the maximum output voltage. The ripple voltage is determined by the size of the capacitor and the current we are pulling out of the supply. Wikipedia pretty much explains it here.

The worst case is where the supply is running in the 15V mode at 5A. To limit the ripple to around 5V we require 10,000uF (10mF) of capacitance.

The issues with selecting the capacitors are:
  • The more capacitance the greater the in-rush current when the supply is turned on
  • Less capacitance means greater ripple, lower output voltage and more dissipation in the pass transistor.
  • Cost. More below.
The bulk capacitor has to be rated for 63V and has to be rated for 105 degrees C operation for longevity. When you add all this up it means expensive capacitors. I found some RS branded 4700uF ones for around $5 each but name brand ones can be as much as $10 each.

Voltage Doubler

As mentioned previously, the plan is to use an N-channel MOSFET as the pass element but this means the gate voltage needs to go up well above the output of the power supply (5-10V). To achieve this I have to either lower the maximal output voltage or find a way to generate this voltage.  The problem with lowering the output apart from wasting the capabilities of the transformer is that it will generate a lot more heat in the MOSFET. So the plan is to use a voltage doubler to generate the gate bias.

The image above shows the basics of the voltage doubler circuit. The AC voltage source models the voltage coming from the transformer and the 1k resistor on the right models the load generated by the gate drive circuit.

The two diodes D1 and D2 together with the two capacitors C1 and C2 form the voltage doubler. The diodes charge the capacitors to the AC peek voltage above or below the other AC rail. The effect is that the total charge across both capacitors is double the input voltage.

With load this will fluctuate greatly so I added D4 and the C4 to smooth the output. Here is the simulated output


You can see we now have around 80V with a few volts of ripple. The gate drive only really needs to be a few volts above the desired output and that will be covered below.

The problem with this circuit is that it doesn't behave well when AC1 and AC2 are connected to a bridge rectifier supplying the main part of the PSU. There is a much simpler circuit that only requires two diodes and two capacitors but initially I had problems simulating this in LTSpice. After some Googling I discovered what I needed to do was to attach a 1M resistor between AC2 and ground as otherwise it things this net is floating. See below - the gate drive is being fed to the 10K resistor (the resistor is acting as a load).


This works as before although it has a little less capacitance so can't supply as much current.


Now we need to keep the gate bias below around 44V (see below) so the easiest thing to do here is to use a transistor with a zener diode as a rudimentary regulator. I can't use a real regulator (like say a LM317) as I can't find one that can go up to 40V. I might change this later but as I don't need any sort of precision here it doesn't matter. Here is the gate bias circuit with regulation:


For some reason. even though the zener's breakdown is listed as 40V it drops around 44V. This is near enough for now.

Regulator

In its most basic form, the regulator is actually quite similar to the dummy load I built before. An op amp compares the voltage at the source of a MOSFET with a set voltage and adjusts the gate voltage so that the source matches the set voltage.

The first problem is that the voltages are quite high. The gate voltage (depending on the MOSFET) could need to be as high as 10V above the source which means 10V above the output or 40V. Lots of op amps can't handle 40V supply rails. I found a couple that can and the first one I tried was a LT6016. Here is the basic circuit with a not-so-carefully chosen MOSFET and some loop compensation. The output of the transformer is 44V which is 30V * SQRT(2). The output is set to 30V and there is a pulsing current load of 5A on the output.


While the output voltage does remain a constant 30V, this circuit has a bunch of limitations. The regulator is really slow - it takes a long time to react to changes in input and in particular to changes where the load drops.

The obvious thing to do is to add some output capacitance to keep the output voltage constant. The one issue with this is that it also tends to hold the output up when the load drops so it also makes sense to add a small bit of permanent load to the output.

This didn't really speed up the response that much even though it did reduce the size of the voltage spike. I then thought that perhaps the problem could be with the current drive to the MOSFET gate. I experimented with push-pull drives but eventually found that a simple emitter follower improved the performance considerably!

Tim on EEVBlog suggested I use a pole-zero compensation on the op-amp. Essentially I added a resistor with the capacitor.

Better Simulation

I want to make sure the regulator is going to be stable pretty much regardless of what you connect to the output of the supply. Importantly, the regulator has to be stable if the load is inductive or capacitive.

Tim on EEVBlog pointed out that modeling the load as a current source is not very useful and it would be better to model as a switch with resistor. In the circuit below I have added a small inductance in series with two resistors and a switch. The switch is controller by a voltage source which opens and closes the switch every 10ms. The resistances are chosen to draw 3A at 30V output and drop back to 1.5A (this is in line with the Agilent PSU specification where they claim the supply recovers to within 15mV of the set voltage within 60us when the load switches from half to full current or vice versa).


I experimented with more or less inductance but found that adding more actually made the response better as it reduce the voltage spikes.

I also discovered a better way to model the input voltage so it includes the inductance of the transformer windings. The way this works is you create two coils and use the K spice directive to specify the coupling between the coils. The voltage ratio is determined by the square of the inductance ratios. See here for a better explanation. 

While experimenting with the closed loop frequency response of the regulator, I realized that the output capacitor has a big effect. In particular the output capacitors ESR will effect the pole created by the capacitor. To model this I added a small series resistance with the output capacitor and chose the resistance from datasheets for similar capacitors on RS.

I experimented with adding large capacitance to the output and in the extreme cases this could make the loop unstable.

Voltage Sense

When the supply is pushing 5A even quite thick wires are likely to have significant losses (a few mV at least). To combat this my plan is to implement a voltage sense system to read the voltage off the front terminals. The circuit as it is currently drawn can sense the positive voltage at the output but if there is resistance in the negative path the output voltage won't take that into account.

To get around this I plan to use an op amp to measure the voltage difference and then use this to drive the regulator control loop. The amplifier has the same compensation that was added to the main voltage regulator error amplifier.


Protection

Other protections I added were:
  • A diode to bypass the MOSFET if the output voltage is higher than the voltage on the bulk capacitor.
  • A zener diode between the source and gate terminals of the MOSFET to ensure that the gate never goes above the MOSFET's Vgs limit.
I was also experimenting with over voltage protection. One issue with adding a larger output capacitor or connecting a heavily capacitive load to the supply is that the MOSFET can't lower the voltage when the load varies. Having a 'down programmer' (as Agilent call it) or otherwise a MOSFET that can short the output when the voltage goes above the limit can help here. The idea is this will blow the fuse in the event of a large battery being connected or the output being connected to mains ground etc.

I had some problems when the output is heavily capacitive although when I added a realistic ESR for the capacitor I found the supply behaved well. I have to think about that a bit.

Circuit So Far

The regulator circuit is still very much a work in progress. My plan (now that I got some parts) is to build some of this and see how it behaves. There may be other problems the simulation doesn't reveal so I think there is no point getting too far until I try building it.



3 comments:

  1. Thanks so much for having this documented, I am learning so much here!

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    Replies
    1. You are welcome! As you can tell I was learning fast while doing this too.

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